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ADVANCE INFORMATION
3797-2*2
MA818
THREE-PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR
The MA818 PWM generator has been designed to provide waveforms for the control of variable speed AC machines, uninterruptible power supplies and other forms of power electronic devices which require pulse width modulation as a means of efficient power control. The six TTL level PWM outputs (Fig. 2) control the six switches in a three-phase inverter bridge. This is usually via an external isolation and amplification stage. Rotational frequency is defined to 12 bits for high accuracy and a zero setting is included in order to implement DC injection braking with no software overhead. Any power waveform can be implemented as this is user-defined in an external PROM/ EPROM. For users requiring an on-chip pre-programmed waveform, the functionally identical MA828 is recommended. Information contained within the pulse width modulated sequences controls the shape, power frequency, amplitude, and rotational direction (as defined by the red-yellow-blue phase sequence) of the output waveform. Parameters such as the carrier frequency, minimum pulse width, and pulse delay time may be defined during the initialisation of the device. The pulse delay time (underlap) controls the delay between turning on and off the two power switches in each output phase of the inverter bridge, in order to accommodate variations in the turn-on and turn-off times of families of power devices. The MA818 is easily controlled by a microprocessor and its fully-digital generation of PWM waveforms gives unprecedented accuracy and temperature stability. Precision pulse shaping capability allows optimum efficiency with any power circuitry. The device operates as a stand-alone microprocessor peripheral, reading the power waveform directly from a PROM/EPROM and requiring microprocessor intervention only when operating parameters need to be changed. An 8-bit multiplexed data bus is used to receive addresses and data from the microprocessor/controller. This is a standard MOTELTM bus, compatible with most microprocessors/controllers. The MA818 is fabricated in CMOS for low power consumption.
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 WR* (R/W) RD* (DS) ALE* (AS) RST CLK CS TRIP ZPP RPHB YPHB BPHB VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
VDD A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 SET TRIP RPHT YPHT BPHT
MA818
31 30 29 28 27 26 25 24 23 22 21
DC40 DG40 DP40
* = Intel bus format = Motorola bus format
AD4 AD3 AD2 AD1 AD0 VDD A10 NC A9 A8 A7
39 38 37 36 35
6
5
4
3
2
1
44 43 42 41 40
AD5 AD6 AD7 WR* (R/W)
7 8 9 10 11 12 13 14 15 16
A6 A5 A4 A3 A2 NC A1 A0 D0 D1 D2
FEATURES s Fully Digital Operation
RD* (DS) NC ALE* (AS) RST CLK CS TRIP
MA818
34 33 32 31 30
s Interfaces with Most Microprocessors s Wide Power-Frequency Range s Carrier Frequency Selectable up to 24kHz s Waveform Stored in External PROM/EPROM s Double Edged Regular Sampling s Selectable Minimum Pulse Width and Underlap Time s DC Injection Braking
MOTEL is a registered Trademark of Intel Corp. and Motorola Corp.
17 29 18 19 20 21 22 23 24 25 26 27 28
ZPP
RPHB
YPHB
BPHB
NC
BPHT
YPHT
RPHT
SET TRIP
VSS
D3
HP44
Fig. 1 Pin connections - top view (not to scale)
MA818
PIN DESCRIPTIONS
Pin.no. DC/DG/DP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin.no. HP44 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Intel: WR Motorola: R/W Intel: RD Motorola: DS Intel: ALE Motorola: AS RST CLK CS TRIP ZPP RPHB YPHB BPHB VSS BPHT YPHT RPHT SET TRIP D3 D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VDD Type I I I I I I I I I I I I I I O O O O O P O O O I I I I I O O O O O O O O O O O P Function Multiplexed Address/Data (LSB) Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data(MSB) Intel bus control: Write Strobe Motorola bus control: Read/Write select Intel bus control: Read Strobe Motorola bus control: Data Strobe Intel bus control: Address Latch Enable Motorola bus control: Address Strobe Reset internal counters, active low Clock input Chip Select input, active low Output trip status; low = output tripped Zero Phase Pulse Red Phase, Bottom power switch Yellow Phase, Bottom power switch Blue Phase, Bottom power switch Negative power supply (0V) Blue Phase, Top power switch Yellow Phase, Top power switch Red Phase, Top power switch Set output trip. 90k internal pull-up resistor Eprom Data (LSB) Eprom Data Eprom Data Eprom Data (MSB) Eprom Address (LSB) Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address Eprom Address (LSB) Positive power supply
2
MA818
RST CS MOTEL INTERFACE

8
BUS CONTROL
RED PHASE
PULSE DELETION PULSE DELAY CIRCUIT RPHT RPHB
SYSTEM BUS AD0-AD7
BUS DEMULTIPLEXER
R0 R1 R2 R3 R4
24-BIT INITIALISATION REGISTER PHASING AND CONTROL LOGIC
YELLOW PHASE
PULSE DELETION PULSE DELAY CIRCUIT YPHT YPHB
24-BIT CONTROL REGISTER
BLUE PHASE
PULSE DELETION PULSE DELAY CIRCUIT BPHT BPHB CLOCK CLOCK DIVIDER ADDRESS DATA GENERATOR BUFFER
11 4
TRIP LATCH
TRIP
A0-A10 D0-D3 TO FROM WAVEFORM STORAGE PROM/EPROM
SET TRIP
Fig. 2 MA818 internal block diagram
FUNCTIONAL DESCRIPTION
An asynchronous method of PWM generation is used with uniform or `double-edged' regular sampling of the waveform stored in the PROM/EPROM as illustrated in Fig.3. The use of an external PROM/EPROM allows the user to define the optimum power waveform for the particular motor being used. The triangle carrier wave frequency is selectable up to 24kHz (assuming the maximum clock frequency of 12.5MHz is used) enabling ultrasonic operation for noise critical applications. Power frequency ranges of up to 4kHz (with 12.5MHz clock) are possible, with the actual output frequency resolved to 12-bit accuracy within the chosen range in order to give precise motor speed control and smooth frequency changing. The output phase sequence of the PWM outputs can also be changed to allow both forward and reverse motor operation. PWM output pulses can be `tailored' to the inverter characteristics by defining the minimum allowable pulse width (the MA818 will delete all shorter pulses from the `pure' PWM pulse train) and the pulse delay (underlap) time without the need for external circuitry. This gives cost advantages in both component savings and in allowing the same PWM circuitry to be used for control of a number of different motor drive circuits simply by changing the microprocessor software. Power frequency amplitude control is also provided with an overmodulation option to assist in rapid motor braking. An asynchronous trip input allows the PWM outputs to be shut down immediately, overriding the microprocessor control in the event of an emergency. Other possible MA818 applications are as a 3-phase waveform generator as part of a switched-mode power supply (SMPS) or of an uninterruptible power supply (UPS). In such applications the high carrier frequency allows a very small switching transformer to be used.
MICROPROCESSOR INTERFACE
The MA818 interfaces to the controlling microprocessor by means of a multiplexed bus of the MOTEL format. This interface bus has the ability to adapt itself automatically to the format and timing of both MOTorola and IntEL interface buses (hence MOTEL). Internally, the detection circuitry latches the status of the DS/RD line when AS/ALE goes high. If the result is high. Then the Intel mode is used; if the result is low then the Motorola mode is used. This procedure is carried out each time that AS/ ALE goes high. In practice this mode selection is transparent to the user. For bus connection and timing information refer to the description relevant to the microprocessor/controller being used. Industry standard microprocessors such as the 8085, 8088, etc. and microcontrollers such as the 8051, 8052 and 6805 are all compatible with the interface on the MA818. This interface consists of 8 data lines, AD0 - AD7 (write only in this instance), which are multiplexed to carry both the address and data information, 3 bus control lines, labelled WR,RD and ALE in Intel mode and R/W, DS and AS in Motorola mode, and a Chip Select input. CS, which allows the MA818 to share the same bus as other microprocessor peripherals. It should be noted that all bus timings are derived from the microprocessor and are independent of the MA818 clock input.
3
MA818
TRIANGLE WAVE AT CARRIER FREQUENCY, SAMPLING ON 1VE AND 2VE PEAKS
PWM SWITCHING INSTANTS 11
0
POWER WAVEFORM AS READ FROM EXTERNAL PROM/EPROM
21 11
RESULTING PWM WAVEFORM
0
21
Fig. 3 Asynchronous PWM generation with`double-edged' regular sampling as used by the MA818
t1
ALE AS
t1
t2
RD
t4 t3 t5 t7
t2
WR
t3
t4
DS
t6 t8 t9
R/W
CS
t8
t10 t11
CS
t9
AD0-AD7
t10
t11
t15
LATCH ADDRESS
t12
LATCH DATA
AD0-AD7
t15
LATCH ADDRESS
t12
LATCH DATA
Fig. 4 Intel bus timing definitions
Parameter ALE high period Delay time, ALE to WR WR low period Delay time, WR high to ALE high CS setup time CS hold time Address setup time Address hold time Data setup time Data hold time Symbol t1 t2 t3 t4 t8 t9 t10 t15 t11 t12 Min. 70 40 200 40 20 0 30 30 100 30 Units ns ns ns ns ns ns ns ns ns ns
Fig. 5 Motorola bus timing definitions
Parameter AS high period Delay time, as low to DS high DS high period Delay time, DS low to AS high DS low period DS high to R/W low setup time R/W hold time CS setup time CS hold time Address setup time Address hold time Write data setup time Write data hold time Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t15 t11 t12 Min. 90 40 210 40 200 10 10 20 0 30 30 110 30 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 1 Intel bus timings at VDD = 5V, TAMB = 125C
Table 2 Motorola bus timings at VDD = 5V, TAMB = 125C
4
MA818
MICROPROCESSOR BUS TIMING Intel Mode (Fig. 4 and Table 1)
The address is latched by the falling edge of ALE. Data is written from the bus into the MA818 on the rising edge of WR. RD is not used in this mode because the registers in the MA818 are write only. However, this pin must be connected to RD (or tied high) to enable the MA818 to select the correct interface format. Power frequency range This sets the maximum power frequency that can be carried within the PWM output waveforms. This would normally be set to a value to prevent the motor system being operated outside its design parameters. Pulse delay time ('underlap') For each phase of the PWM cycle there are two control signals, one for the top switch connected to the positive inverter DC supply and one for the bottom switch connected to the negative inverter DC supply. In theory, the states of these two switches are always complementary. However, due to the finite and non-equal turn-on and turn- off times of power devices, it is desirable when changing the state of the output pair, to provide a short delay time during which both outputs are off in order to avoid a short circuit through the switching elements. Pulse deletion time A pure PWM sequence produces pulses which can vary in width between 0% and 100% of the duty cycle. Therefore, in theory, pulse widths can become infinitesimally narrow. In practice this causes problems in the power switches due to storage effects and therefore a minimum pulse width time is required. All pulses shorter than the minimum specified are deleted. Counter reset This facility allows the internal power frequency counter of the MA818 to be set to zero, disabling the normal frequency control and giving a 50% output duty cycle.
Motorola Mode (Fig. 5 and Table 2)
The address is latched on the falling edge of the AS line. Data is written from the bus into the MA818 (only when R/W is low) on the falling edge of DS (providing CS is low).
CONTROLLLNG THE MA818
The MA818 is controlled by loading data into two 24-bit registers via the microprocessor interface. These registers are the initialisation register and the control register. The initialisation register would normally be loaded before motor operation (i.e., prior to the PWM outputs being activated) and sets up the basic operating parameters associated with the motor and inverter. This data would not normally be updated during motor operation. The control register is used to control the PWM outputs (and hence the motor) during operation e.g., stop/start, speed, forward/reverse etc. and would normally be loaded and changed only after the initialisation register has been loaded. As the MOTEL bus interface is restricted to an 8-bit wide format, data to be loaded into either of the 24-bit register is first written to three 8-bit temporary registers R0, R1 and R2 before being transferred to the desired 24-bit register. The data is accepted (and acted upon) only when transferred to one of the 24-bit registers. Transfer of data from the temporary registers to either the initialisation register or the control register is achieved by a write instruction to a dummy register. Writing to dummy register R3 results in data transfer from R0, R1 and R2 to the control register, while writing to dummy register R4 transfers data from R0, R1 and R2 to the initialisation register. It does not matter what data is written to the dummy registers R3 and R4 as they are not real registers. It is merely the write instruction to either of these registers which is acted upon in order to load the initialisation and control registers. AD2 0 0 0 0 1 AD1 0 0 1 1 0 AD0 0 0 0 0 1 Register R0 R1 R2 R3 R4 Comment Temporary register R0 Temporary register R1 Temporary register R2 Transfers control data Transfers initialisation data
Initialisation Register Programming
The initialisation register data is loaded in 8-bit segments into the three 8-bit temporary registers R0-R2. When all the initialisation data has been loaded into these registers it is transferred into the 24-bit initialisation register by writing to the dummy register R4. FRS2 FRS1 FRS0 X X CFS2 CFS2 CFS2

FREQUENCY RANGE SELECT WORD FRS2 = MSB FRS0 = LSB
DON'T CARE
Fig. 6 Temporary register R1 Carrier frequency selection The carrier frequency is a function of the externally applied clock frequency and a division ratio n, determined by the 3-bit CFS word set during initialisation. The values of n are selected as shown in Table 4.
CFS word Value of n 101 32 100 16 011 8 010 4 001 2 000 1
Table 3 MA818 register addressing
Initialisation Register Function
The 24-bit initialisation register contains parameters which, under normal operation, will be defined during the power-up sequence. These parameters are particular to the drive circuitry used, and therefore changing these parameters during a PWM cycle is not recommended. Information in this register should only be modified while RST is active (i.e. low) so that the PWM outputs are inhibited (low) during the updating process. The parameters set in the initialisation register are as follows: Carrier frequency Low carrier frequencies reduce switching losses whereas high carrier frequencies increase waveform resolution and can allow ultrasonic operation.
Table 4 Values of clock division ratio n The carrier frequency, fCARR, is then given by: fCARR = k 5123n
where k = clock frequency and n = 1, 2, 4, 8, 16 or 32 (as set by CFS) Power frequency range selection The power frequency range selected here defines the maximum limit of the power frequency. The operating power frequency is controlled by the 12-bit Power Frequency Select (PFS) word in the control register but may not exceed the value set here.

CARRIER FREQUENCY SELECT WORD CFS2 = MSB CFS0 = LSB
5
MA818
The power frequency range is a function of the carrier waveform frequency (fCARR) and a multiplication factor m, determined by the 3-bit FRS word. The value of m is determined as shown in Table 5. FRS word Value of m 110 64 101 32 100 16 011 8 010 4 001 2 000 1
CR
PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0
COUNTER RESET
Table 5 Values of carrier frequency multiplicaion factor m The power frequency range, fRANGE, is then given by: f fRANGE = CARR 3 m 384 where fCARR = carrier frequency and m = 1, 2, 4, 8, 16, 32 or 64 (as set by CFS).
X
X
PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
DON'T CARE
PULSE DELAY SELECT WORD PDY5 = MSB PDY0 = LSB
Pulse deletion time To eliminate short pulses the true PWM pulse train is passed through a pulse deletion circuit. The pulse deletion circuit compares pulse widths with the pulse deletion time set in the initialisation register. lf a pulse (either positive or negative) is greater than or equal in duration to the pulse deletion time, it is passed through unaltered, otherwise the pulse is deleted. The pulse deletion time, tpd , is a function of the carrier wave frequency and pdt, defined by the 7-bit pulse deletion time word (PDT). The value of pdt is selected as shown in Table 7. PDT word Value of pdt 1111111 1111110 1 2 ...etc... ...etc... 0000000 128

Fig. 7 Temporary register R2
Pulse delay time The pulse delay time affects all six PWM outputs by delaying the rising edges of each of the outputs by an equal amount. The pulse delay time is a function of the carrier waveform frequency and pdy, defined by the 6-bit pulse delay time select word (PDY). The value of pdy is selected as shown in Table 6. PDY word Value of pdy 111111 1 111110 2 ...etc... ...etc... 000000 64

The pulse deletion time, tpd, is then given by: pdt tpd = fCARR3512 where pdt = 1-128 (as set by PDT) and fCARR = carrier frequency. Fig. 10 shows the effect of pulse deletion on a pure PWM waveform. Counter reset When the CR bit is active (i.e., Iow) the internal power frequency phase counter is set to 0 degrees for the red phase. The power frequency is then set to 0Hz and cannot be changed via the normal frequency control.
Table 6 Values of pdy
The pulse delay time, tpdy, is then given by: pdy tpdy = fCARR3512 where pdy = 1- 64 (as set by PDY) and fCARR = carrier frequency. Fig 8 shows the eftect of the pulse delay circuit. It should be noted that as the pulse delay circuit follows the pulse deletion circuit (see Fig. 2), the minimum pulse width seen at the PWM outputs will be shorter than the pulse deletion time set in the initialisation register. The actual shortest pulse generated is given by tpd 2tpdy.
PWM SIGNAL REQUIRED AT INVERTER OUTPUT
Control Register Function
This 24-bit register contains the parameters that would normally be modified during PWM cycles in order to control the operation of the motor. The parameters set in the control register are as follows: Power frequency (speed) Allows the power frequency of the PWM outputs to be adjusted within the range specified in the initialisation register Forward/reverse Allows the direction of rotation of the AC motor to be changed by changing the phase sequence of the PWM outputs. Power frequency amplitude By altering the widths of the PWM output pulses while maintaining their relative widths, the amplitude of the power waveform is effectively altered whilst maintaining the same power frequency. Overmodulation Allows the output waveform amplitude to be doubled so that a quasi-squarewave is produced. A combination of overmodulation and a lower power frequency can be used to achieve rapid braking in AC motors. Output inhibit Allows the outputs to be set to the low state while the PWM generation continues internally. Useful for temporarily inhibiting the outputs without having to to change other register contents.
tpdy
OUTPUT SIGNAL TO DRIVE TOP SWITCH INVERTER ARM
tpdy
tpdy
OUTPUT SIGNAL TO DRIVE BOTTOM SWITCH INVERTER ARM
tpdy
tpdy = PULSE DELAY TIME
Fig. 8 Effect of pulse delay on PWM pulse train
6

PULSE DELETION TIME SELECT WORD PDT6 = MSB PDT0 = LSB
Fig. 9 Temporary register R0
Table 7 Values of pdt
MA818
PWM SIGNAL BEFORE PULSE DELETION
.tpd ,tpd
PWM SIGNAL AFTER PULSE DELETION
.tpd .tpd
.tpd .tpd
.tpd ,tpd
.tpd .tpd
PULSE DELETED
PULSE DELETED
tpd = PULSE DELETION TIME
Fig. 10 The effect of the pulse deletion circuit
Control Register Programming
The control register should only be programmed once the initialisation register contains the basic operating parameters of the MA818. As with the initialisation register, control register data is loaded into the three 8-bit temporary registers R0 - R2. When all the data has been loaded into these registers it is transferred into the 24-bit control register by writing to the dummy register R3. It is recommended that all three temporary registers are updated before writing to R3 in order to ensure that a conformal set of data is transferred to the control register for execution. Output inhibit selection When active (i.e., Iow) the output inhibit bit INH sets all the PWM outputs to the off (low) state. No other internal operation of the device is affected. When the inhibit is released the PWM outputs continue immediately. Note that as the inhibit is asserted after the pulse deletion and pulse delay circuits, pulses shorter than the normal minimum pulse width may be produced initially. Overmodulation selection The overmodulation bit OM is, in effect, the ninth bit (MSB) of the amplitude word. When active (i.e., high) the output waveform will be controlled in the 100% to 200% range by the amplitude word. The percentage amplitude control is now given by: Overmodulated Amplitude = APOWER 3 100% where APOWER = the power amplitude
V
PFS7 PFS6 PFS5 PFS4 PFS3 PFS2 PFS1 PFS0

POWER FREQUENCY SELECT WORD BITS 0-7 PFS0 = LSB
Fig. 11 Temporary register R0
0
t
F/R
OM
INH
X DON'T CARE
PFS11 PFS10 PFS9 PFS8

OVERMODULATION BIT 0 = DISABLED 1 = ACTIVE FORWARD/ REVERSE BIT 0 = FORWARD 1 = REVERSE
POWER FREQUENCY SELECT WORD BITS 8-11 PFS11 = MSB
V
OVERMODULATION BIT NOT SET (100% MODULATION)
OUTPUT INHIBIT BIT 0 = DISABLED 1 = ACTIVE
0
t
Fig. 12 Temporary register R1
Power frequency selection The power frequency is selected as a proportion of the power frequency range (defined in the initialisation register) by the 12bit power frequency select word, PFS, allowing the power frequency to be defined in 4096 equal steps. As the PFS word spans the two temporary registers R0 and R1 it is therefore essential, when changing the power frequency, that both these registers are updated before writing to R3. The power frequency (fPOWER) is given by:
OVERMODULATION BIT SET (200% MODULATION)
Fig. 13 Voltage waveforms as seen at the motor terminals, showing the effect of setting the overmodulation bit
Forward/ reverse selection The phase sequence of the three-phase PWM output waveforms is controlled by the Forward/Reverse bit F/R. The actual effect of changing this bit from 0 (forward) to 1 (reverse) is to reverse the power frequency phase counter from incrementing the phase angle to decrementing it. The required output waveforms are all continuous with time during a forward/ reverse change. In the forward mode the output phase sequence is redyellow-blue and in the reverse mode the sequence is blueyellow-red.
fRANGE 3 pfs 4096 where pfs = decimal value of the 12-bit PFS word and fRANGE = power frequency range set in the initialisation register. fPOWER =
7
MA818
However, the value of pdy must be an integer. As the purpose of the pulse delay is to prevent `shoot-through' (where both top and bottom arms of the inverter are on simultaneously), it is sensible to round the pulse delay time up to a higher, rather than a lower figure. Thus, if we assign the value 16 to pdy this gives a delay time of 5*2s. From Table 6, pdy = 16 corresponds to a 6-bit PDY word of 110000 in temporary register R2. 4. Setting the pulse deletion time In setting the pulse deletion time (i.e., the minimum pulse width) account must be taken of the pulse delay time, as the actual minimum pulse width seen at the PWM outputs is equal to tpd2tpdy. Therefore, the value of the pulse deletion time must, in this instance, be set 5*2s longer than the minimum pulse length required Minimum pulse length required = 10s tPD to be set to 10s15*2s = 15*2s Now, pdt tpd = fCARR3512
AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0
Amplitude selection The power wavefortm amplitude is determined by scaling the amplitude of the waveform samples stored in the external PROM/EPROM by the value of the 8-bit amplitude select word (AMP). The percentage amplitude control is given by: A Power Amplitude, APOWER = 3 100% 225 where A = decimal value of AMP.
MA818 PROGRAMMING EXAMPLE
The following example assumes that a master clock of 12*288 MHz is used (12*288 MHz crystals are readily available). This clock frequency will allow a maximum carrier frequency of 24 kHz and a maximum power frequency of 4 kHz.

AMPLITUDE SELECT WORD AMP7 = MSB AMP0 = LSB
Fig.14 Temporary register R2
pdt = fpd3fCARR3512
= 15*2310263631033512 = 46*7 Again, pdt must be an integer and so must be either rounded up or down - the choice of which will depend on the application. Assuming we choose in this case the value 46 for pdt, this gives a value of tpd, of 15 s and an actual minimum pulse width of 1525*2s = 9*8s. From Table 7, pdt = 46 corresponds to a value of PDT, the 7bit word in temporary register R0 of 1010010. The data which must be programmed into the three temporary registers R0, R1 and R2 (for transter into the initialisation register) in order to achieve the parameters in the example given, is shown in Fig. 15.
Initialisation Register Programming Example
A power waveform range of up to 250Hz is required with a carrier frequency of 6kHz, a pulse deletion time of 10s and an underlap of 5s. 1. Setting the carrier frequency The carrier frequency should be set first as the power frequency, pulse deletion time and pulse delay time are all defined relative to the carrier frequency. We must calculate the value of n that will give the required carrier frequency: k fCARR = 5123n
Temporary Register R0 1 CR 1 0 1 0 0 1 0
n=
k = =4 5123fCARR 512363103
12*2883106
From Table 4, n = 4 corresponds to a 3-bit CFS word of 010 in temporary register R1. 2. Setting the power frequency range We must calculate the value of m that will give the required power frequency: f fRANGE = CARR 3 m 384
PDT6 PDT5 PDT4 PDT3 PDT2 PDT1 PDT0 Temporary Register R1
1
0
0
X X
X X
0
1
0
FRS2 FRS1 FRS0
CFS2 CFS2 CFS2
m=
fRANGE3384 fCARR
=
2503384 63103
= 16 X X X X
Temporary Register R2 1 1 0 0 0 0
From Table 5, m = 16 corresponds to a 3-bit FRS word of 100 in temporary register R1. 3. Setting the pulse delay time As the pulse delay time affects the actual minimum pulse width seen at the PWM outputs, it is sensible to set the pulse delay time before the pulse deletion time, so that the effect of the pulse delay time can be allowed for when setting the pulse deletion time. We must calculate the value of pdy that will give the required pulse delay time:
PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
Fig. 15
pdy fCARR3512 pdy = tpdy3fCARR3512 tpdy =
= 5310263631033512 = 15*4
8
MA818
Control Register Programming Example
The control register would normally be updated many times while the motor is running, but just one example is given here. It is assumed that the initialisation register has already heen programmed with the parameters given in the previous example. A power waveform of 100Hz is required with a PWM waveform amplitude of 80% of that stored in the EPROM. The phase sequence should be set to give forward motor rotation.The outputs should be enabled and no overmodulation is required. 1. Setting the power frequency The power frequency, fPOWER, can be selected to 12-bit accuracy (i.e 4096 equal steps) from 0Hz to fRANGE as defined in the initialisation register. In this case, with fRANGE = 250Hz, the power frequency can be adjusted in increments of 0*06Hz.
POWER ON
RST 0
fRANGE 3 pfs 4096 f 34096 10034096 pfs = POWER = = 1638*4 fRANGE 250 fPOWER =
We can only have pfs as an integer, so if we assign pfs = 1638 this gives fPOWER = 99.97 Hz.The 12-bit binary equivalent of this value gives a PFS word of 011001100110 in temporary registers R0 and R1. 2. Setting overmodulation, forward/reverse, output inhibit Overmodulation is not required therefore OM = 0. Forward motor control is required (i.e., the phase sequence of the PWM outputs should be red-yellow-blue) therefore forward/reverse bit F/R = 0. Output inhibit should be inactive (i e., the outputs should be active), therefore INH= 1. These bits are all set in temporary register R1. 3. Setting the power waveform amplitude A APOWER = 3 100% 225 A 3255 803255 A = POWER = = 204 100 100 The 8-bit binary equivalent of this value gives an AMP word of 11001100 in temporary register R2. The data which must be programmed into the three temporary registers R0, R1 and R2 (for transfer into the control register) in order to achieve the parameters in the example given, is shown in Fig. 16. Temporary Register R0 0 1 1 0 0 0 1 1
WRITE INITIALISATION DATA

WRITE R0 WRITE R1 WRITE R2 WRITE R4
WRITE R0 WRITE R1 WRITE R2 WRITE R3
WRITE TO CONTROL REGISTER INHIBITING PWM OUTPUTS BEFORE COMPLETING RESET CYCLE
ENABLE PWM OUTPUTS
RST 1
WRITE CONTROL DATA

WRITE R0 WRITE R1 WRITE R2 WRITE R3
PFS7 PFS6 PFS5 PFS4 PFS3 PFS2 PFS1 PFS0 Temporary Register R1 0 F/R 0 OM 1 INH X X 0 1 1 0
NO
CHANGE CONTROL DATA ? NO
YES
PFS11 PFS10 PFS9 PFS8
CHANGE INITIALISATION DATA ? YES
Temporary Register R2 1 1 0 0 1 1 0 0
AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0
Fig. 16
Fig. 17 Typical MA818 programming routine
9
MA818
HARDWARE INPUT/OUTPUT FUNCTIONS Set Output Trip (SET TRIP input)
The SET TRIP input is provided separately from the microprocessor interface in order to allow an external source to override the microprocessor and provide a rapid shutdown facility. For example, logic signals from overcurrent sensing circuitry or the microprocessor `watchdog' might be used to activate this input. When the SET TRIP input is taken to a logic high, the output trip latch is activated. This results in the TRIP output and the six PWM outputs being latched low immediately. This condition can only be cleared by applying a reset cycle to the RST input. Because of the asynchronous nature of the SET TRIP input, it is important that when not in use it is tied low and isolated from potential sources of noise. On no account should this input be left floating. Waveform segment 0- 60 60*23- 120 120*23- 179*77 Sample number 0 - 255 256 - 511 512 - 767
Table 8 180 of the 360 cycle is divided into 768 8-bit samples
255
POWER WAVEFORM VALUE OF 8-BIT SAMPLE
Output Trip Status (TRIP output)
The TRIP output indicates the status of the output trip latch and is active low.
Reset (RST input)
The RST input performs the following functions when activbe (low): 1. All PWM outputs are forced low (if not already low) thereby turning off the drive switches. 2. All internal counters are reset to zero (this corresponds to 0 for the red phase output). 3. The rising edge of RST reactivates the PWM outputs resetting the output trip and setting the TRIP output high - assuming that the SET TRIP input is inactive (i.e. Iow).
0 0 90 PHASE (768-BIT RESOLUTION) 180
Fig. 18 180 sample of typical power waveform
WAVEFORM STORAGE
An industry standard 2K38 PROM or EPROM (2716 or 27C16) is required for waveform storage. As less than half the memory capacity of the PROM/EPROM is needed to store the waveform, this is used to advantage in order to minimise the pin count of the MA818. Each 8-bit data word representing a sample of the waveform is stored as two 4-bit nibbles in the least significant nibble position of the 8-bit PROM/EPROM locations. Hence the most significant nibble is unused (and may therefore be left unprogrammed) so only 4 data lines (D0 - D3) are required. The 768 waveform samples are therefore stored as 1546 four-bit samples. Fig. 19 illustrates the method used for mapping the data into the PROM/EPROM. The least signiflcant nibbles are stored sequentially from location 0H to 300H, and the most significant nibbles are stored from 400H to 700H. The MA818 reads Ihe data by accessing the two 4-bit nibbles (using A10 to select the high and low nibble memory areas) and then concatenates them internally to form the 8-bit waveform sample byte. The reading of data from the the PROM/EPROM is performed automatically by the MA818 without microprocessor intervention whenever the PWM generation is active.
800H 700H NOT USED 400H 300H L.S. NIBBLES 0000H M.S. NIBBLES
Zero Phase Pulse (ZPP output)
The ZPP output provides pulses at the same frequency as the power frequency with a 1 : 2 mark-space ratio. When in the forward mode of operation the falling edge of ZPP corresponds to 0 for the red phase PWM output. In the reverse mode, the rising edge of ZPP corresponds to 0 for the red phase PWM output.
Clock (CLK input)
The CLK input provides a timing reference used by the MA818 for all timings related to the PWM outputs. The microprocessor interface, however, derives all its timings from the microprocessor and therefore the microprocessor and the MA818 may be run either from the same or from different clocks.
PWM WAVEFORM ASSIGNMENT
The waveform amplitude data used to construct the PWM output sequences is read by the MA818 from an external 2K38 PROM/EPROM. The use of an external PROM/EPROM allows the user to define the exact waveform required.
Waveform Definition
Good waveform resolution is achieved by storing 768 8-bit amplitude samples representing the positive 180 span of the waveform. It is assumed that the data is symmetrical about the 90 axis. The MA818 constructs the full 360 waveform by assigning negative values to the same samples for the second half of the cycle. It uses these samples to calculate the three instantaneous amplitudes for all three phases. The 768 8- bit samples are linearly spaced over the 0 to 180 span, giving an angular resolution of approximately 0*23
D7
D3
D0
Fig. 19 Waveform PROM/EPROM memory map
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MA818
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated): VDD = 15V65%, TAMB = 125C
DC Characteristics
Characteristic Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Supply current (static) Supply current (dynamic) Supply voltage Symbol VIH VIL IIN VOH VOL IDD (static) IDD (dynamic) VDD 4*75 ,10 5*0 4*0 .4*5 ,0*2 0*4 100 20 7*5 Value Min. Typ. Max. 2 0*8 10 Units V V A V V A mA V VIN = VSS or VDD IOH = 24mA IOL = 4mA All outputs open circuit fCLK = 10MHz Conditions
NOTE 1. The SET TRIP input has an internal pull-up resistor with an approximate value of 90k
AC Characteristics
Characteristic Clock frequency SET TRIP = 0 outputs tripped TRIP = 0 EPROM address to output delay tACC Symbol fCLK tTRIP ,1 ,1 Value Min. Typ. Max. 12*5 3 3 450 Units MHz s s ns Conditions M : S ratio = 1 : 1 620%
NOTE 2. For microprocessor interface timings, see Intel and Motorola bus timings (Tables 1 and 2).
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD 10V VSS20*3V to VDD10*3V Voltage on any pin Current through any I/O pin 610mA Storage temperature 265C to 1125C Operating temperature range 0C to 170C The temperature ranges quoted apply to all package types. Many package types are available and extended temperature ranges can be offered on some. Further information is available on request. Stresses above those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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MA818
INVERTER
1
RECTIFIER AND SMOOTHING R Y B SINGLE OR 3-PHASE POWER SUPPLY 3-PHASE VARIABLE VOLTAGE, VARIABLE FREQUENCY WAVEFORM DC LINK 3-PHASE AC INDUCTION MOTOR
2
6
ISOLATOR TTL LEVEL PWM WAVEFORMS D0-D7 A0-A10
15
6
FAST SHUTDOWN
WAVEFORM PROM/EPROM
MA818
SYSTEM MONITOR (ADC)
DATA/ADDRESS BUS (AD0-AD7)
8
DISPLAY HANDLING
KEYBOARD HANDLING
MICROPROCESSOR
STATIC RAM
ROM (PROGRAM STORAGE)
I
I9 7.5H Z
Fig. 20 A typical MA818 application
12
MA818
13
MA818
14
MA818
PACKAGE DETAILS
Dimensions are shown thus: mm (in)
1
PIN 1 REF NOTCH
12*95/15*75 (0*510/0*620)
15*24 (0*6) NOM CTRS
40 51*31 (2*020) MAX 0*51 (0*02) MIN 5*08/(0*20) MAX
0*20/0*30 (0*008/0*012)
1*37 (0*054) NOM.
0*36/0*51 (0*014/0*20)
40 LEADS AT 2*54 (0*10) NOM. SPACING
3*18/4*06 (0*125/0*160)
This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information.
40-LEAD SIDEBRAZED CERAMIC DIL (DILMON) - DC40
1
12*70/15*75 (0*500/0*620)
PIN 1 REF NOTCH
15.24 (0*6) NOM CTRS
40 53*34 (2*10) MAX 0*20/0*36 (0*008/0*014)
5*59/(0*220) MAX
0*51 (0*02) 3*05 (0*120) MIN MIN
0*36/0*58 (0*015/0*23)
40 LEADS AT 2*54 (0*10) NOM. SPACING
40-LEAD CERAMIC DIL - DG40
This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information.
Continued...
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MA818
PACKAGE DETAILS (Continued)
1
14*73 (0*58) MAX
PIN 1 REF NOTCH
15.24 (0*6) NOM CTRS
40 1*14/1*65 (0*045/0*107) 5*59/(0*220) MAX 53*34 (2*10) MAX 0*51 (0*02) 3*05 (0*120) MIN MIN 0*23/0*41 (0*009/0*016)
0*38/0*61 (0*015/0*24)
40 LEADS AT 2*54 (0*10) NOM. SPACING
40-LEAD PLASTIC DIL - DP40
PIN 1 PIN 1 REF. SIDE
This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information.
0*508 (0*02) NOM.
PIN 1 REF. CORNER 1*14 (0*045) NOM. 345
1*14 (0*045) NOM. 345
OPTIONAL PIN 1 REFERENCE
0*66/0*81 (0*026/0*032)
1*27 (0*050) NOM. SPACING
4*19/4*70 (0*165/0*185)
12*7 (0*5) NOM.
11*27/11*78 (0*444/0*464)
12*32/12*37 (0*485/0*487)
0*33/0*53 (0*013/0*021)
14*98/16*00 (0*59/0*63)
44-LEAD QUAD PLASTIC QUAD J-LEAD - HP44
This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information.
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, CA95067-0017 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES q FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F Fax : (1) 64 46 06 07 q GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55 q ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 q JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 q NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. q SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 q SWEDEN Stockholm Tel: 4687029770 Fax: 4686404736 q UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1993 Publication No. DS3797 Issue No. 2.2 October 1993
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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